1. Field of the Invention
The present invention relates to a test apparatus and a testing method reducing a required bandwidth for a memory provided in a test apparatus.
2. Description of Related Art
A test apparatus is designed to test a device under test (DUT) based on a test program. Specifically, the test apparatus sequentially reads and executes commands of the test program from a memory. Then, the test apparatus reads a test pattern corresponding to each command from the memory to output the pattern to each terminal of the device under test. As a result, an output pattern output from the device under test is compared with a predetermined expectation pattern, which is a pattern to be output from the device under test.
Here, since a related patent document is not known, a description of which is omitted.
As described above, the test apparatus reads each command of the test program, the test pattern, and the expectation pattern from the memory during really operating the test program. Then, it is desirable that these data are stored on one common main memory, in order to utilize memory capacity of the memory effectively. In this case, the main memory must realize a bandwidth capable of reading the command, the test pattern, and the expectation pattern during really operating the device under test.
On the other hand, when the failure of the device under test is detected according to the result of the test, a user may want to analyze the output pattern in order to investigate the cause. In order to realize this, it is desirable to store the output pattern on the main memory. However, in order to read the command, the test pattern, and the expectation pattern and also write the output pattern in the main memory, it is necessary to further raise the bandwidth of the main memory, thereby increasing the cost of the test apparatus.